The present invention relates to semiconductor design technology, and in particular, to an internal voltage generator of a semiconductor device that operates stably even in a low power supply voltage environment. More particularly, the present invention relates to a voltage detecting circuit of an internal voltage generator that operates stably even in a low power supply voltage environment.
Most semiconductor devices, including dynamic random access memories (DRAMs), generate and use not only an external power supply voltage (e.g., VDD and VSS) but also an internal voltage having a different level than the power supply voltage. In general, the internal voltage is generated by a charge pumping mode or a voltage down converting mode by using an external power supply voltage VDD, an external ground voltage VSS and a reference voltage corresponding to the target level of the internal voltage.
A high-level voltage VPP and a back-bias voltage VBB are examples of the internal voltage of the DRAM generated by the charge pumping mode. Also, a core voltage VCORE and a bitline precharge voltage VBLP are examples of the internal voltage of the DRAM generated by the voltage down converting mode.
The high-level voltage VPP has a higher voltage level than the external power supply voltage VDD, which is generally used to drive a wordline. On the other hand, the back-bias voltage VBB is a negative voltage lower than the external ground voltage VSS, which is generally used as a body (or bulk) bias of a cell transistor (e.g., an NMOS transistor).
FIG. 1 is a block diagram of a conventional back-bias voltage (VBB) generator. Referring to FIG. 1, the conventional back-bias voltage generator includes a back-bias reference voltage generating unit 50, a back-bias voltage detector 10, an oscillator 20, a pump controller 30, and a charge pump 40. The back-bias reference voltage generating unit 50 is configured to receive an external power supply voltage VDD to perform a voltage down converting operation on the basis of the voltage level of a reference voltage VREF to generate a back-bias reference voltage VREFB that maintains a predetermined target level. The back-bias voltage detector 10 is configured to receive the back-bias reference voltage VREFB and a back-bias voltage VBB, which is fed back from a back-bias voltage output terminal, to output an enable signal BBEb. The oscillator 20 is configured to output an oscillation signal OSC with a predetermined oscillation frequency in response to the enable signal BBEb. The pump controller 30 is configured to receive the oscillation signal OSC to generate a pump control signal PUMP_CTRL. The charge pump 40 is configured to perform a negative charge pumping operation on the back-bias voltage output terminal in response to the pump control signal PUMP_CTRL.
Herein, the reference voltage VREF always maintains the predetermined target level regardless of a temperature change and a voltage level change of the external power supply voltage VDD. In general, the reference voltage VREF is generated by a bandgap reference circuit that operates by receiving the external power supply voltage VDD.
When a power supply voltage is externally applied to stabilize the voltage level of the external power supply voltage VDD above a predetermined level, a power-up signal is activated to initiate the voltage generating operation of all the internal voltage generators including the back-bias voltage generator and the bandgap reference circuit. The back-bias voltage output terminal has a ground voltage (VSS) level before the initiation of the voltage generating operation of the back-bias voltage generator. The back-bias voltage detector 10 detects the ground voltage level of the back-bias voltage output terminal to activate the enable signal BBEb to a logic low level, thereby enabling the oscillator 20. When the oscillator 20 is enabled to output the oscillation signal OSC with the predetermined oscillation frequency, the pump controller 30 receives the oscillation signal OSC to generate the pump control signal PUMP_CTRL and the charge pump 40 performs a negative charge pumping operation in response to the pump control signal PUMP_CTRL. This charge pumping operation continues until the voltage level of the back-bias voltage output terminal reaches the target level determined according to the back-bias reference voltage VREFB.
Conventionally, the back-bias voltage detector 10 of FIG. 1 includes a back-bias voltage normal detector, a back-bias voltage modulation detector, a back-bias voltage high clamping detector, and a back-bias voltage low clamping detector, and a detection signal combination circuit. The back-bias voltage normal detector is configured to detect the voltage level of the back-bias voltage VBB that is constant independent of a temperature change. The back-bias voltage modulation detector is configured to detect the voltage level of the back-bias voltage VBB that is linearly dependent on a temperature change. The back-bias voltage high clamping detector is configured to detect the highest (absolute) clamping level of the back-bias voltage VBB that is constant independent of a temperature change. The back-bias voltage low clamping detector is configured to detect the lowest (absolute) clamping level of the back-bias voltage VBB that is constant independent of a temperature change. The detection signal combination circuit is configured to combine detection signals, which are outputted respectively from the back-bias voltage modulation detector, the back-bias voltage high clamping detector, and the back-bias voltage low clamping detector, to generate a combined detection signal.
FIG. 2 is a circuit diagram of the back-bias voltage detector 10 of FIG. 1, which includes a back-bias voltage normal detector 10A, a back-bias voltage modulation detector 10B, a back-bias voltage high clamping detector 10C, and a back-bias voltage low clamping detector 10D, and a detection signal combining unit 10E.
Referring to FIG. 2, the back-bias voltage normal detector 10A includes a first PMOS transistor P1, a second PMOS transistor P2, and a first inverter INV1. The first PMOS transistor P1 has a gate connected to receive a ground voltage VSS, a source and a bulk connected to receive a back-bias reference voltage VREFB, and a drain connected to a first detection node NODE_1. The second PMOS transistor P2 has a gate connected to receive a back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the first detection node NODE_1. The first inverter INV1 is configured to have an input terminal, which is connected to the first detection node NODE_1, to output a normal detection signal DET_N.
The back-bias voltage modulation detector 10B includes a third PMOS transistor P3, an NMOS transistor N1, and a second inverter INV2. The third PMOS transistor P3 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a second detection node NODE_2. The NMOS transistor N1 has a gate connected to receive the back-bias reference voltage VREFB, a source and a bulk connected to receive the back-bias voltage VBB, and a drain connected to the second detection node NODE_2. The second inverter INV2 is configured to have an input terminal, which is connected to the second detection node NODE_2, to output a modulation detection signal DET_T.
The back-bias voltage high clamping detector 10C includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a third inverter INV3. The fourth PMOS transistor P4 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a third detection node NODE_3. The fifth PMOS transistor P4 has a gate connected to receive the back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the third detection node NODE_3. The third inverter INV3 is configured to have an input terminal, which is connected to the third detection node NODE_3, to output a high clamping detection signal DET_H.
The back-bias voltage low clamping detector 10D includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a fourth inverter INV4. The sixth PMOS transistor P6 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a fourth detection node NODE_4. The seventh PMOS transistor P7 has a gate connected to receive the back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the fourth detection node NODE_4. The fourth inverter INV4 is configured to have an input terminal, which is connected to the fourth detection node NODE_4, to output a low clamping detection signal DET_L.
Herein, since the back-bias voltage normal detector 10A, the back-bias voltage high clamping detector 10C, and the back-bias voltage low clamping detector 10D always have constant back-bias voltage detection levels regardless of a temperature change, they may be implemented in the same circuit configuration. However, since the back-bias voltage normal detector 10A, the back-bias voltage high clamping detector 10C, and the back-bias voltage low clamping detector 10D must have different target back-bias voltage detection levels, their NMOS or PMOS transistors must be different in size.
That is, the sizes of the NMOS or PMOS transistors of the back-bias voltage normal detector 10A are set to detect a back-bias voltage target level value between the back-bias voltage detection level of the back-bias voltage high clamping detector 10C and the back-bias voltage detection level of the back-bias voltage low clamping detector 10D.
The detection signal combining unit 10E includes a first selecting unit 12E, a signal combining unit 14E, and a second selecting unit 16E.
The first selecting unit 12E is configured to select the normal detection signal DET_N outputted from the back-bias voltage normal detector 10A of the modulation detection signal DET_T outputted from the back-bias voltage modulation detector 10B according to a first test signal TEST1 and a fuse option (not illustrated) and output the selected signal as an uncombined detection signal DET_S. The signal combining unit 14E is configured to combine the high clamping detection signal DET_H outputted from the back-bias voltage high clamping detector 10C, the uncombined detection signal DET_S outputted from the first selecting unit 12E, and the low clamping detection signal DET_L outputted from the back-bias voltage low clamping detector 10D to generate a combined detection signal DET_CLP. Herein, the combined detection signal DET_CLP is used to detect the voltage level of the back-bias voltage VBB, whose back-bias voltage detection level varies linearly, in response to the uncombined detection signal DET_S in an intermediate-temperature range, to detect the lowest (absolute) clamping level of the constant back-bias voltage VBB in response to the low clamping detection signal DET_L in a low-temperature (deep cold) range lower than the intermediate-temperature range, and to detect the highest (absolute) clamping level of the constant back-bias voltage VBB in response to the high clamping detection signal DET_H in a high-temperature (deep hot) range higher than the intermediate-temperature range. The second selecting unit 16E is configured to select the uncombined detection signal DET_S or the combined detection signal DET_CLP according to a second test signal TEST2 and a fuse option (not illustrated) and output the selected signal as an enable signal BBEb.
FIG. 3A is a characteristic diagram illustrating a temperature-dependent back-bias voltage (VBB) detection level change in each of the detectors 10A, 10B, 10C and 10D of FIG. 2. FIG. 3B is a characteristic diagram illustrating a change in the back-bias voltage (VBB) detection level clamped by the back-bias voltage detector 10 of FIG. 2.
Referring to FIG. 3A, it can be seen that the normal detection signal DET_N outputted from the back-bias voltage (VBB) normal detector 10A, the high clamping detection signal DET_H outputted from the back-bias voltage (VBB) high clamping detector 10C, and the low clamping detection signal DET_L outputted from the back-bias voltage (VBB) low clamping detector 10D detect the voltage level of the back-bias voltage VBB on the basis of a specific target level even in a temperature change.
On the other hand, it can be seen that a target level for detection of the voltage level of the back-bias voltage VBB for the modulation detection signal DET_T outputted from the back-bias voltage (VBB) modulation detector 10B varies according to a temperature change. That is, it can be seen that the voltage level of the back-bias voltage VBB is detected on the basis of a relatively low target level (absolute value) at a relatively low temperature whereas the voltage level of the back-bias voltage VBB is detected on the basis of a relatively high target level (absolute value) at a relatively high temperature.
Referring to FIG. 3B, it can be seen that the characteristics of the enable signal BBEb outputted to the oscillator 20 vary according to the temperature ranges due to the operation of the detection signal combining unit 10E.
When the normal detection signal DET_N (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E of the detection signal combining unit 10, the enable signal BBEb with characteristics determined according to the normal detection signal DET_N is outputted regardless of the operations of the signal combining unit 14E and the second selecting unit 16E. That is, if the voltage level (absolute value) of the back-bias voltage VBB is higher than the normal target level (absolute value) determined by the back-bias voltage normal detector 10A, both of the logic levels of the normal detection signal DET_N and the enable signal BBEb become high; and if the voltage level (absolute value) of the back-bias voltage VBB is lower than the determined normal target level (absolute value), both of the logic levels of the normal detection signal DET_N and the enable signal BBEb become low. In this case, as illustrated in the drawings, since the normal target level (absolute value) does not change according to a temperature change, the logic level of the enable signal BBEb is not affected by the temperature change.
On the other hand, when the modulation detection signal DET_T (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E and the uncombined detection signal DET_S (among the uncombined detection signal DET_S and the combined detection signal DET_DLP) is selected and outputted as the enable signal BBEb by the second combining unit 16E, the enable signal BBEb with characteristics determined according to the modulation detection signal DET_T is outputted. That is, if the voltage level (absolute value) of the back-bias voltage VBB is higher than the modulation target level (absolute value) determined by the back-bias voltage modulation detector 10B, both of the logic levels of the modulation detection signal DET_T and the enable signal BBEb become high; and if the voltage level (absolute value) of the back-bias voltage VBB is lower than the determined modulation target level (absolute value), both of the logic levels of the modulation detection signal DET_T and the enable signal BBEb become low. In this case, as illustrated in the drawings, since the modulation target level (absolute value) changes according to a temperature change, the logic level of the enable signal BBEb is affected by the temperature change.
When the modulation detection signal DET_T (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E and the combined detection signal DET_CLP (among the uncombined detection signal DET_S and the combined detection signal DET_DLP) is selected and outputted as the enable signal BBEb by the second combining unit 16E, the enable signal BBEb with characteristics determined according to a combination of the modulation detection signal DET_T, the high clamping detection signal DET_H and the low clamping detection signal DET_L is outputted. That is, if the voltage level (absolute value) of the back-bias voltage VBB becomes lower than the lowest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the low clamping detection signal DET_L regardless of the logic level of the modulation detection signal DET_T; if the voltage level (absolute value) of the back-bias voltage VBB becomes higher than the highest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the high clamping detection signal DET_H regardless of the logic level of the modulation detection signal DET_T; and if the voltage level (absolute value) of the back-bias voltage VBB lies between the lowest (absolute) clamping level of the back-bias voltage VBB and the highest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the modulation detection signal DET_T.
The conventional back-bias voltage generator can control the target level of the back-bias voltage VBB by means of the back-bias voltage detector 10 at the desire of a user even when the internal temperature of the semiconductor device changes.
However, the premise that the voltage level of the back-bias reference voltage VREFB supplied to the back-bias voltage detector 10 must always maintain the predetermined target level regardless of a temperature change or an external power supply voltage (VDD) level change, must be satisfied so that the back-bias voltage detector 10 of the conventional back-bias voltage generator can operate as described above.
If the voltage level of the external power supply voltage VDD supplied to the semiconductor device is sufficiently high, the above premise can be satisfied by the bandgap reference circuit that is used to generate the reference voltage VREF.
However, when the voltage level of the external power supply voltage VDD supplied to the semiconductor device decreases further according to the requirements for a low-power operation of the semiconductor device, the above premise fails to be satisfied, which causes the following problems.
FIG. 4 is a characteristic diagram illustrating a back-bias voltage (VBB) level change depending on an external power supply voltage (VDD) level change in the conventional back-bias voltage generator. Referring to FIG. 4, it can be seen that the voltage level of the back-bias reference voltage VREFB for the reference voltage VREF is determined at a different point as the voltage level of the external power supply voltage VDD increases.
That is, it can be seen that the reference voltage VREF with a relatively low target voltage level of 0.75 V increases along with the external power supply voltage VDD before the voltage level of the external power supply voltage VDD exceeds a voltage level of 0.75 V, but the reference voltage VREF continues to maintain the target voltage level without any more voltage level increase after the voltage level of the external power supply voltage VDD exceeds the voltage level of 0.75 V.
On the other hand, it can be seen that the back-bias reference voltage VREFB with a relatively high target voltage level of 1.5 V must increase along with the external power supply voltage VDD until the voltage level of the external power supply voltage VDD reaches a voltage level of 1.5 V, and the back-bias reference voltage VREFB continues to maintain the target voltage level without any more voltage level increase after the voltage level of the external power supply voltage VDD exceeds the voltage level of 1.5 V.
Herein, as described above, the back-bias voltage detector 10 of the conventional back-bias voltage generator receives the back-bias reference voltage VREFB to perform an operation of detecting the voltage level of the back-bias voltage VBB. Therefore, as illustrated in the drawings, the voltage level of the back-bias voltage VBB detected by the back-bias voltage detector 10 changes as the voltage level of the back-bias reference voltage VREFB changes.
Specifically, it can be seen that the voltage level of the back-bias voltage VBB fails to maintain a predetermined target level and changes with a change in the voltage level of the back-bias reference voltage VREFB in a period A before the voltage level of the back-bias reference voltage VREFB reaches a predetermined target level, and the back-bias voltage VBB maintains the predetermined target level in a period B after the voltage level of the back-bias reference voltage VREFB reaches the predetermined target level.
Herein, it can be seen that the voltage level of a first back-bias voltage VBB@COLD of the back-bias voltage VBB increases with an increase in the voltage level of the back-bias reference voltage VREFB, whereas the voltage level of a second back-bias voltage VBB@HOT of the back-bias voltage VBB decreases with an increase in the voltage level of the back-bias reference voltage VREFB. The reason for this is that the back-bias voltage normal detector 10A and the back-bias voltage modulation detector 10B have different operational characteristics as the voltage level of the back-bias reference voltage VREFB changes.
In general, the MOS transistors of the back-bias voltage normal detector 10A operate in a saturation state when the back-bias reference voltage VREFB increases. Therefore, the back-bias voltage normal detector 10A performs a detecting operation so that the absolute value of the back-bias voltage VBB can increase further. Also, the MOS transistors of the back-bias voltage modulation detector 10B operate in a linear state when the back-bias reference voltage VREFB increases. Therefore, the back-bias voltage modulation detector 10B performs a detecting operation so that the absolute value of the back-bias voltage VBB can decrease further. Of course, the back-bias voltage high clamping detector 10C and the back-bias voltage low clamping detector 10D have the same characteristics as the back-bias voltage normal detector 10A.
Thus, the first back-bias voltage VBB@COLD will be the back-bias voltage VBB generated according to the detecting operation of the back-bias voltage modulation detector 10B, and the second back-bias voltage VBB@HOT will be the back-bias voltage VBB generated according to the detecting operation of the back-bias voltage normal detector 10A.
Due to these characteristics, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A can perform the opposite detecting operations. As illustrated in the drawings, such a feature becomes more apparent as the voltage level of the back-bias reference voltage VREFB increases. It can be seen that the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A can stably perform the completely opposite detecting operations after the voltage level of the back-bias reference voltage VREFB reaches the predetermined target level.
However, as the voltage level of the external power supply voltage VDD supplied to the semiconductor device decreases further according to the requirements for a low-power operation of the semiconductor device, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A cannot perform the opposite detecting operations, so that the separate configuration of the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A becomes meaningless.
That is, as illustrated in the graph of FIG. 4, if the voltage level of the external power supply voltage VDD becomes 1 V, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A perform the detecting operations with the same characteristics, so that it is unnecessary to provide the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A separately.
Actually, an external power supply voltage VDD with a voltage level of 2.5 V is supplied for a DDR DRAM; an external power supply voltage VDD with a voltage level of 1.8 V is supplied for a DDR2 DRAM; an external power supply voltage VDD with a voltage level of 1.5 V is supplied for a DDR3 DRAM; and an external power supply voltage VDD with a voltage level of 1.2 V is supplied for a DDR4 DRAM that is developed recently.
When this trend is analyzed on the basis of the graph of FIG. 4, it can be seen that the DDR DRAM, the DDR1 DRAM, the DDR2 DRAM and the DDR3 DRAM can be stably operated using the conventional back-bias voltage generating circuit, but the DDR4 DRAM cannot be stably operated even using the conventional back-bias voltage generating circuit.
As described above, because the voltage level of the external power supply voltage VDD continues to decrease with the development of new semiconductor devices, there is a possibility that the voltage level of the external power supply voltage VDD may decrease below 1 V. If a new semiconductor device operated by an external power supply voltage VDD with a voltage level of below 1 V is developed, the new semiconductor device cannot operate according to the intention of a designer even when using the conventional back-bias voltage generating circuit, so that it is difficult to expect the normal operation.